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DS1236 micromanager chip DS1236 022698 1/19 features ? holds microprocessor in check during power transients ? halts and restarts an out-of-control microprocessor ? monitors pushbutton for external override ? warns microprocessor of an impending power failure ? converts cmos sram into nonvolatile memory ? unconditionally write protects memory when power supply is out of tolerance ? consumes less than 100 na of battery current at 25 c ? controls external power switch for high current applications ? accurate 10% power supply monitoring ? optional 5% power supply monitoring designated DS1236-5 ? provides orderly shutdown in nonvolatile microprocessor applications ? supplies necessary control for low-power astop modeo in battery operated hand-held applications ? standard 16-pin dip or space-saving 16-pin soic ? optional industrial temperature range -40 c to +85 c pin assignment in vbat vcco vcc gnd pf rc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rst rst pbrst cei ceo st nmi pf wc/sc 16-pin dip (300 mil.) see mech. drawings section 1 11 12 13 14 2 3 4 5 6 7 8 9 10 15 16 vbat vcco vcc gnd pf pf wc/sc rc rst rst pbrst cei ceo st nmi in 16-pin soic (300 mil.) see mech. drawings section pin description v bat +3 volt battery input v cco switched sram supply output v cc +5 volt power supply input gnd ground pf power fail (active high) pf power fail (active low) wc/sc wake-up control (sleep) rc reset control in early warning input nmi non-maskable interrupt st strobe input ceo chip enable output cei chip enable input pbrst pushbutton reset input rst reset output (active low) rst reset output (active high) description the DS1236 micromanager chip provides all the nec- essary functions for power supply monitoring, reset control, and memory backup in microprocessor-based systems. a precise internal voltage reference and com- parator circuit monitor power supply status. when an out-of-tolerance condition occurs, the microprocessor reset and power fail outputs are forced active, and static ram control unconditionally write protects external memory. the DS1236 also provides early warning de- tection of a user-defined threshold by driving a non-maskable interrupt. external reset control is pro- vided by a pushbutton reset input which is debounced and activates reset outputs. an internal watchdog timer can also force the reset outputs to the active state if the strobe input is not driven low prior to watchdog time-out. reset control and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and start-up in battery backup and battery operated applica- tions. a block diagram of the DS1236 is shown in figure 1.
DS1236 022698 2/19 pin description pin name description v bat +3v battery input provides nonvolatile operation of control functions. v cco v cc output for nonvolatile sram applications. v cc +5v primary power input. pf power fail indicator, active high, used for external power switching as shown in figure 9. pf power fail indicator, active low. wc/sc wake-up and sleep control. invokes low-power mode. rc reset control input. determines reset output . normally low for nmos processors and high for battery-backed cmos processors. in early warning power fail input. this voltage sense point can be tied (via resistor divider) to a user-selected voltage. nmi non-maskable interrupt. used in conjunction with the in pin to indicate an impending power failure. st strobe input. a high-to-low transition will reset the watchdog timer, indicating that software is still in control. ceo chip enable output. used with nonvolatile sram applications. cei chip enable input. pbrst pushbutton reset input. rst active low reset output. rst active high reset output. processor mode a distinction is often made between cmos and nmos processor systems. in a cmos system, power con- sumption may be a concern, and nonvolatile operation is possible by battery backing both the sram and the cmos processor. all resources would be maintained in the absence of v cc . a power-down reset is not issued since the low-power mode of most cmos processors (stop) is terminated with a reset. a pulsed interrupt (nmi ) is issued to allow the cmos processor to invoke a sleep mode to save power. for this case, a power-on re- set is desirable to wake up and initialize the processor. the cmos mode is invoked by connecting rc to v cco . an nmos processor consumes more power, and con- sequently may not be battery backed. in this case, it is desirable to notify the processor of a power fail, then keep it in reset during the loss of v cc . this avoids inter- mittent or aberrant operation. on power-up, the proces- sor will continue to be reset until v cc reaches an opera- tional level to provide an orderly start. the nmos mode is invoked by connecting rc to ground. power monitor the DS1236 employs a band gap voltage reference and a precision comparator to monitor the 5-volt supply (v cc ) in microprocessor-based systems. when an out-of-tolerance condition occurs, the rst and rst outputs are driven to the active state. th e v cc trip point (v cctp ) is set for 10% operation so that the rst and rst outputs will become active as v cc falls below 4.5 volts (4.37 typical). the v cctp for the 5% operation op- tion (DS1236-5) is set for 4.75 volts (4.62 typical). the rst and rst signals are excellent for microprocessor reset control, as processing is stopped at the last possi- ble moment of in-tolerance v cc . on power-up, the rst and rst signals are held active for a minimum of 25 ms (100 ms typical) after v cctp is reached to allow the power supply and microprocessor to stabilize. note: the operation described above is obtained with the re- set control pin (rc) connected to gnd (nmos mode). please review the reset control section for more infor- mation.
DS1236 022698 3/19 watchdog timer the DS1236 provides a watchdog timer function which forces the rst and rst signals to the active state when the strobe input (st ) is not stimulated for a predeter- mined time period. this time period is 400 ms typically with a maximum time-out of 600 ms. the watchdog time-out period begins as soon as rst and rst are in- active. if a high-to-low transition occurs at the st input prior to time-out, the watchdog timer is reset and begins to time out again. the st input timing is shown in figure 2. to guarantee the watchdog timer does not time out, a high-to-low transition on st must occur at or less than 100 ms (minimum time-out) from a reset. if the watchdog timer is allowed to time out, the rst and rst outputs are driven to the active state for 25 ms mini- mum. the st input can be derived from microprocessor address, data, and/or control signals. under normal op- erating conditions, these signals would routinely reset the watchdog timer prior to time-out. if the watchdog tim- er is not required, two methods have been provided to disable it. permanently grounding the in pin in the cmos mode (rc=1) will disable the watchdog. in normal operation with rc=1, the watchdog is disabled as soon as the in pin is below v tp . with in grounded, an nmi output will occur only at power-up, or when the st pin is strobed. as shown in the figure 3, a falling edge on st will gener- ate an nmi when in is below v tp . this allows the pro- cessor to verify that power is between v tp and v cctp , as an nmi will be returned immediately after the st strobe. the watchdog timer is not affected by the in pin when in nmos mode (rc=0). if the nmi signal is required to monitor supply voltages, the watchdog may also be disabled by leaving the st in- put open. independent of the state of the rc pin, the watchdog is also disabled as soon as v cc falls to v cctp . pushbutton reset an input pin is provided on the DS1236 for direct con- nection to a pushbutton. the pushbutton reset input re- quires an active low signal. internally, this input is pulled high by a 10k resistor whenever v cc is greater than v bat . the pbrst pin is also debounced and timed such that the rst and rst outputs are driven to the active state for 25 ms minimum. this 25 ms delay begins as the pushbutton is released from a low level. a typical ex- ample of the power monitor, watchdog timer, and push- button reset connections are shown in figure 4. the pbrst input is disabled whenever the in pin voltage level is less than v tp and the reset control (rc) is tied high (cmos mode). the pbrst input is also disabled whenever v cc is below v bat . timing of the pbrst -gen- erated rst is illustrated in figure 5. non-maskable interrupt the DS1236 generates a non-maskable interrupt nmi for early warning of power failure to a microprocessor. a precision comparator monitors the voltage level at the in pin relative to a reference generated by the internal band gap. the in pin is a high impedance input allowing for a user-defined sense point. an external resistor volt- age divider network (figure 6) is used to interface with high voltage signals. this sense point may be derived from the regulated 5-volt supply or from a higher dc voltage level closer to the main system power input. since the in trip point v tp is 2.54 volts, the proper val- ues for r1 and r2 can be determined by the equation as shown in figure 6. proper operation of the DS1236 re- quires that the voltage at the in pin be limited to v in . therefore, the maximum allowable voltage at the supply being monitored (v max ) can also be derived as shown in figure 6. a simple approach to solving this equation is to select a value for r2 high enough to keep power con- sumption low, and solve for r1. the flexibility of the in input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for microprocessor shut-down between nmi and rst or rst . when the supply being monitored decays to the voltage sense point, the DS1236 pulses the nmi output to the active state for a minimum of 200 m s. the nmi power fail detection circuitry also has built-in time domain hystere- sis. that is, the monitored supply is sampled periodical- ly at a rate determined by an internal ring oscillator run- ning at approximately 30 khz (33 m s/cycle). three consecutive samplings of out-of-tolerance supply (be- low v sense ) must occur at the in pin to activate nmi . therefore, the supply must be below the voltage sense point for approximately 100 m s or the comparator will re- set. in this way, power supply noise is removed from the monitoring function, preventing false trips. during a power-up , any in pin levels below v tp are disabled from reaching the nmi pin until v cc rises to v cctp . as a result, any potential nmi pulse will not be initiated until v cc reaches v cctp . removal of an active low level on the nmi pin is con- trolled by either an internal time-out (when in pin is less than v tp ) or by the subsequent rise of the in pin above
DS1236 022698 4/19 v tp . the initiation and removal of the nmi signal during power-up results in an nmi pulse of from 0 m s minimum to 500 m s maximum, depending on the relative voltage relationship between v cc and the in pin voltage. as an example, when the in pin is tied to ground during pow- er-up, the internal time-out will result in a pulse of 200 m s minimum to 500 m s maximum. in contrast, if the in pin is tied to v cco during power-up, nmi will not produce a pulse on power-up. note that a fast slewing power sup- ply may cause the nmi to be virtually non-existent on power-up. this is of no consequence, however, since a rst will be active. DS1236 functional block diagram figure 1 v cc digital digital time out level sense 2.54v in st vbat rc rst pf reset 30khz ring internal bandgap wake/sleep pbrst cei nmi rst ce control pf ceo wc/sc v cco sampler oscillator reference digital sampler control delay control clock control
DS1236 022698 5/19 if the in pin is connected to v cco , the nmi output will pulse low as v cc decays to v cctp in the nmos mode (rc=0). in the cmos mode (rc=v cco ) the pow- er-down of v cc out-of-tolerance at v cctp will not pro- duce a pulse on the nmi pin. given that any nmi pulse has been completed by the time v cc decays to v cctp , the nmi pin will remain high. the nmi voltage will follow v cc down until v cc decays to v bat . once v cc decays to v bat , the nmi pin will either remain at v ohl or enter tri-state mode as determined by the rc pin (see areset controlo section). memory backup the DS1236 provides all of the necessary functions re- quired to battery back a static ram. first, a switch is provided to direct sram power from the incoming 5 volt supply (v cc ) or from an external battery (v bat ), which- ever is greater. this switched supply (v cco ) can also be used to battery back a cmos microprocessor. for more information about nonvolatile processor applications, review the areset controlo and awake controlo sections. second, the same power fail detection described in the power monitor section is used to hold the chip enable output (ceo ) to within 0.3 volts of v cc or to within 0.7 volts of v bat . this write protection mechanism occurs as v cc falls below v cctp as specified. if cei is low at the time power fail detection occurs, ceo is held in its present state until cei is returned high, or the period t ce expires. this delay of write protection until the current memory cycle is completed prevents the corruption of data. if ceo is in an inactive state at the time of v cc fail detection, ceo will be unconditionally disabled within t cf . during nominal supply conditions ceo will follow cei with a maximum propagation delay of 20 ns. figure 7 shows a typical nonvolatile sram application. freshness seal in order to conserve battery capacity during storage and/or shipment of an end system, the DS1236 pro- vides a freshness seal to electrically disconnect the bat- tery. figure 8 depicts the three pulses below ground on the in pin required to invoke the freshness seal. the freshness seal will be disconnected and normal opera- tion will begin when v cc is cycled and reapplied to a lev- el above v bat . to prevent negative pulses associated with noise from setting the freshness mode in system applications, a se- ries diode and resistor can be used to shunt noise to ground. during manufacturing, the freshness seal can still be set by holding tp2 at -3 volts while applying the 0 to -3 volt clock to tp1. power switching when larger operating currents are required in a bat- tery-backed system, the 5-volt supply and battery sup- ply switches internal to the DS1236 may not be large enough to support the required load through v cco with a reasonable voltage drop. for these applications, the pf and pf outputs are provided to gate external power switching devices. as shown in figure 9, power to the load is switched from v cc to battery on power-down, and from battery to v cc on power- up. the ds1336 is designed to use the pf output to switch between v bat and v cc . it provides better leakage and switchover per- formance than currently available discrete components. the transition threshold for pf and pf is set to the exter- nal battery voltage v bat , allowing a smooth transition between sources. the load applied to the pf pin from the external switch will be supplied by the battery. therefore, if a discrete switch is used, this load should be taken into consideration when sizing the battery. reset control as mentioned above, the DS1236 supports two modes of operation. the cmos mode is used when the system incorporates a cmos microprocessor which is battery backed. the nmos mode is used when a non-battery backed processor is incorporated. the mode is se- lected by the rc (reset control) pin. the level of this pin distinguishes timing and level control on rst, rst , and nmi outputs for volatile processor operation versus nonvolatile battery backup or battery-operated proces- sor applications.
DS1236 022698 6/19 st/input timing figure 2 st v ih t st t td nmi/from st/input figure 3 in nmi st t stn v oh t nmi t ipd v tp v il v ol v oh
DS1236 022698 7/19 power monitor, watchdog figure 4 gnd rc rst rst port 1 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 pbrst st v cc +3 v dc +5 v dc DS1236 8051 up v bat push button reset timing figure 5 rst pbrst rst v il v ih t pb t rst v oh v ol
DS1236 022698 8/19 non-maskable interrupt figure 6 4.80 = r1 + 10k 10k x 2.54 r1 = 8.9k ohm r1 + 10k 10k x 2.54 9.00 = r1 = 25.4k ohm v = 9.00 2.54 x 5.00 = 17.7 volts gnd rc rst voltage r1 r2 to microprocessor in rst DS1236 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +3v dc +5v dc nmi v bat v cc max example 1: 5 volt supply, r2 = 10k ohm, v sense = 4.80 volts example 2: 12 volt supply, r2 = 10k ohm, v sense = 9.00 volts sense point nonvolatile sram figure 7 gnd rc rst +3v from decoder 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cei ceo ce rst v bat v cco v cc +5v dc v cc sram DS1236 to m p
DS1236 022698 9/19 when the rc pin is tied to ground, the DS1236 is de- signed to interface with nmos processors which do not have the microamp currents required during a battery backed mode. grounding the rc pin does, however, continue to support nonvolatile backup of system sram memory. nonvolatile systems incorporating nmos processors generally require that only the sram memory and/or timekeeping functions be battery backed. when the processor is not battery backed (rc = 0), all signals connected from the processor to the DS1236 are disconnected from the backup battery sup- ply, or grounded when system v cc decays below v bat . in the nmos processor system, the principal emphasis is placed on giving early warnings with nmi , then provid- ing a continuously active rst and rst signal during power-down while isolating the backup battery from the processor during a loss of v cc . during power-down, nmi will pulse low for a minimum of 200 m s, and then return high. if rc is tied low (nmos mode), the voltage on nmi will follow v cc until v cc sup- ply decays to v bat , at which point nmi will enter tri-state (see timing diagram). also, upon v cc out-of-tolerance at v cctp , the rst and rst outputs are driven active and rst will follow v cc as the supply decays. on pow- er-up, rst follows v cc up, rst is held low, and both re- main active for t rst after valid v cc . during a power-up from a v cc voltage below v bat , any detected in pin lev- els below v tp are disabled from reaching the nmi pin until v cc rises to v cctp . as a result, any potential nmi pulse will not be initiated until v cc reaches v cctp . re- moval of an active low level on the nmi pin is controlled by either an internal time-out (when the in pin is less than v tp ), or by the subsequent rise of the in pin above v tp . the initiation and removal of the nmi signal results in an nmi pulse of 0 m s minimum to 500 m s maximum during power-up, depending on the relative voltage rela- tionship between v cc and the in pin. as an example, when the in pin is tied to ground, the internal time-out will result in a pulse of 200 m s minimum to 500 m s maxi- mum. in contrast, if the in pin is tied to v cco , nmi will not produce a pulse on power-up. connecting the rc pin to a high (v cco ) invokes cmos mode and provides nonvolatile support to both the sys- tem sram as well as a low power cmos processor. when using cmos microprocessors, it is possible to place the microprocessor into a very low- power mode termed the astopo or ahalto mode. in this state the cmos processor requires only microamp currents and is fully capable of being battery backed. this mode generally allows the cmos microprocessor to maintain the con- tents of internal ram as well as state control of i/o ports during battery backup. the processor can subsequently be restarted by any of several different signals. to main- tain this low-power state, the DS1236 issues no nmi and/or reset signals to the processor until it is time to bring the processor back into full operation. to support the low-power processor battery backed mode (rc = 1), the DS1236 provides a pulsed nmi for early power fail- ure warning. waiting to initiate a stop mode until after the nmi pin has returned high will guarantee the proces- sor that no other active nmi or rst/rst will be issued by the DS1236 until one of two conditions occurs: 1) vol- tage on the pin rises above v tp , which activates the watchdog, or 2) v cc cycles below then above v bat , which also results in an active rst and rst . if v cc does not fall below v cctp , the processor will be re- started by the reset derived from the watchdog timer as the in pin rises above v tp . with the rc pin tied to v cco , rst and rst are not forced active as v cc collapses to v cctp . the rst is held at a high level via the external battery as v cc falls below battery potential. this mode of operation is in- tended for applications in which the processor is made nonvolatile with an external source, and allows the pro- cessor to power down into a stop mode as signaled from nmi at an earlier voltage level. the nmi output pin will pulse low for t nmi following a low voltage detect at the in pin of v tp . following t nmi , however, nmi will also be held at a high level (v bat ) by the battery as v cc de- cays below v bat . on power-up, rst and rst are held inactive until v cc reaches v bat , then rst and rst are driven active for t rst . if the in pin falls below v tp during an active reset, the reset outputs will be forced inactive by the nmi output. in addition, as long as the in pin is less than v tp , stimulation of the st pin will result in addi- tional nmi pulses. in this way, the st pin can be used to allow the cmos processor to determine if the supply voltage, as monitored by the in pin, is above or below a selected operating value. this is illustrated in figure 3. as discussed above, the rc pin determines the timing relationships and levels of several signals. the follow- ing section describes the power-up and power-down timing diagrams in more detail. timing diagrams this section provides a description of the timing dia- grams shown in figure 10, figure 11, figure 12, and figure 13. these diagrams show the relative timing and levels in both the nmos and the cmos mode for pow- er-up and down. figure 10 illustrates the relationship for
DS1236 022698 10/19 power-down in cmos mode. as v cc falls, the in pin voltage drops below v tp . as a result, the processor is notified of an impending power failure via an active nmi , which allows it to enter a sleep mode. as the power falls further, v cc crosses v cctp , the power monitor trip point. since the DS1236 is in cmos mode, no reset is generated. the rst voltage will follow v cc down, but will fall no further than v bat . at this time, ceo is brought high to write protect the ram. when the v cc reaches v bat , a power fail is issued via the pf and pf pins. figure 11 illustrates operation of the power-down se- quence in nmos mode. once again, as power falls, an nmi is issued. this gives the processor time to save crit- ical data in nonvolatile sram. when v cc reaches v cctp , an active rst and rst are given. the rst volt- age will follow v cc as it falls. ceo , pf, and pf will oper- ate in a similar manner to cmos mode. notice that the nmi will tri-state to prevent a loss of battery power. figure 12 shows the power-up sequence for the nmos mode. as v cc slews above v bat , the pf and pf pins are deactivated. an active reset occurs as well as an nmi . although the nmi may be short due to slew rates, reset will be maintained for the standard t rst time-out period. at a later time, if the in pin falls below v tp , a new nmi will occur. if the processor does not issue a st , a watchdog reset will also occur. the second nmi and rst are provided to illustrate these possibilities. figure 13 illustrates the power-up timing for cmos mode. the principal difference is that the DS1236 is- sues a reset immediately in the nmos mode. in cmos mode, a reset is issued when in rises above v tp . de- pending on the processor type, the nmi may terminate the stop mode in the processor. wake control/sleep control the wake/sleep control input (wc/sc ) allows the pro- cessor to disable all comparators on the DS1236 before entering the stop mode. this feature allows the DS1236, processor, and static ram to maintain nonvo- latility in the lowest power mode possible. the proces- sor may invoke the sleep mode in battery-operated applications to conserve battery capacity when an ab- sence of activity is detected. the operation of this signal is shown in figure 14. the DS1236 may subsequently be restarted by a high-to-low transition on the pbrst input through human interface via a keyboard, touch- pad, etc. the processor will then be restarted as the watchdog times out and drives rst and rst active. the DS1236 can also be started up by forcing the wc/sc pin high from an external source. also, if the DS1236 is placed in a sleep mode by the processor and system power is lost, the DS1236 will wake up the next time v cc rises above v bat . these possibilities are illus- trated in figure 15. when the sleep mode is invoked during normal pow- er-valid conditions, all operation on the DS1236 is dis- abled, thus leaving the nmi , rst, and rst outputs dis- abled as well as the st and in inputs. however, a loss of power during a sleep mode will result in an active rst and rst when the rc pin is grounded (nmos mode). if the rc pin is tied high, the rst and rst pins will remain inactive during power-down in a sleep mode. removal of the sleep mode by the pbrst input is not affected by the in pin threshold at v tp when the rc pin is tied high (cmos mode). subsequent power-up of the v cc sup- ply with the rc pin tied high will activate the rst and rst outputs as the main supply rises above v bat . a high-to-low transition on the wc/sc pin must follow a high-to-low transition on the st pin by t wc to invoke a sleep mode for the DS1236.
DS1236 022698 11/19 freshness seal figure 8 note: this series of pulses must be applied during normal +5 volt operation. from voltage sense point 100 ohms 0 volts 1 ms in -3 volts in tp1 tp2 power switching figure 9 gnd +3v from pf battery rst gnd pf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 pf rst cei ceo 9 10 11 12 13 14 15 16 DS1236 ds1336 v bat v cco v cc out5 in5 in2 in4 out4 v bat02 v cc /in1 out1 out2 out3 v bat01 in3 +5v dc to sram v cc v batin to m p decoder to sram pf
DS1236 022698 12/19 cmos mode power-down (rc = v cco ) figure 10 rst = 0v 4.5 4.25 rst pf nmi rst ceo cei pf rst = v ohl v cc = v cctp v cc = v bat t cf v ol v il v ih t pd t ppf in pin + v tp v cc = 0v nmi = v ohl nmi = 0v ceo = v ohl ceo = 0v cei pf = v ohl pf v oh t ipd t nmi t f v cc v ol v oh v oh
DS1236 022698 13/19 nmos mode power-down (rc = gnd) figure 11 4.5 4.25 rst pf nmi rst ceo cei v cc = v cctp v cc = v bat t cf v ol v il v ih t pd t ppf v cc = 0v nmi = tri-state nmi = 0v ceo = v ohl ceo = 0v pf = v ohl v oh t ipd t nmi t f v cc cei pf pf rst = 0v rst slews with v cc in pin = v tp t rpd v oh v ol v oh
DS1236 022698 14/19 nmos mode power-up (rc = gnd) figure 12 4.5 4.25 rst rst cei v cc = v cctp v cc = v bat v ol v il v ih t pd t ppf v cc = 0v nmi = tri-state ceo = v ohl ceo = 0v pf = v ohl v oh t ipd t nmi pf in pin = v tp t r t nmi t ipd v ol v ol v oh t rst t rec t rpu v oh v oh v ol
DS1236 022698 15/19 cmos mode power-up (rc = v cco ) figure 13 4.5 4.25 rst = 0v rst = v ohl v cc = v cctp v cc = v bat v ol v il v ih t ppf in pin = v tp v cc = 0v nmi = v ohl nmi = 0v ceo = v ohl ceo = 0v cei pf = v ohl pf v oh t ipd t nmi t nmi v oh v ol v oh t ipd t r t pd t rec t arst t brst t nrt t rst v ol
DS1236 022698 16/19 wake/sleep control figure 14 st v ih v il t st wc/sc v il t wc options for invoking wakeup figure 15 sleep mode invoked sleep mode removed v ih v il t st pbrst wc/sc v ih v il v bat v cc v bat
DS1236 022698 17/19 absolute maximum ratings* voltage on v cc pin relative to ground -0.5v to +7.0v voltage on i/o relative to ground 0.5v to v cc + 0.5v voltage on in pin relative to ground 3.5v to v cc + 0.5v operating temperature 0 c to 70 c operating temperature (industrial version) 40 c to +85 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 supply voltage (5% option) v cc 4.75 5.0 5.5 v 1 input high level v ih 2.0 v cc +0.3 v 1 input low level v il -0.3 +0.8 v 1 in input pin v in -0.3 v cc +0.3 v 1 battery input v bat 2.7 4.0 v 1 dc electrical characteristics (0 c to 70 c; v cc = 4.5 v to 5.5v) parameter symbol min typ max units notes supply current i cc 4 ma 2 sleep supply current in sleep mode i cc 20 m a battery current i bat 0.1 m a 2 supply output current (v cco =v cc - 0.3v) i cc01 100 ma 3 supply output current in data retention (v cc < v bat ) i cc02 1 ma 4 supply output voltage v cco v cc 0.3 v 1 battery backup voltage v cco v bat 0.7 v 1,6 low level @ rst v ol 0.4 v 1 output voltage @ 500 m a v oh v cc 0.5v v cc 0.1v v 1 ceo and pf output v ohl v bat 0.7 v 1,6 pbrst pull up resist r pbrst 10k ohms input leakage current i li -1.0 +1.0 m a 18 output leakage i lo -1.0 +1.0 m a 18 output current @0.4v i ol 4.0 ma 12
DS1236 022698 18/19 parameter notes units max typ min symbol output current @2.4v i oh -1.0 ma 13 power sup. trip point v cctp 4.25 4.37 4.50 v 1 power supply trip (5% option) v cctp 4.50 4.62 4.75 v 1 in input pin current i ccin -1.0 +1.0 m a in input trip point v tp 2.5 2.54 2.6 v 1 ac electrical characteristics (0 c to 70 c; v cc = 4.5v to 5.5v) parameter symbol min typ max units notes v cc fail detect to rst, rst t rpd 40 100 175 m s v tp to nmi t ipd 40 100 175 m s reset active time t rst 25 100 150 ms nmi pulse width t nmi 200 300 500 m s 14 st pulse width t st 20 ns 19 pbrst @ v il t pb 30 ms v cc slew rate 4.75 to 4.25 t f 300 m s chip enable propagation delay t pd 20 ns v cc fail to chip enable high t cf 7 12 44 m s 17 v cc valid to rst, rst (rc=1) t fpu 100 ns v cc valid to rst & rst t rpu 25 100 150 ms 5 v cc slew to 4.24 to v bat t fb1 10 m s 7 v cc slew 4.25 to 4.75 v bat t fb2 100 m s 8 chip enable output recovery time t rec .1 m s 9 v cc slew 4.25 to 4.75 t r 0 m s chip enable pulse width t ce 5 s 10 watchdog time delay t td 100 400 600 ms st to wc/sc t wc 0.1 50 m s v bat detect to pf, pf t ppf 2 m s 7 st to nmi t stn 30 ns 11 nmi to rst & rst t nrt 30 ns v bat detect to rst & rst t arst 200 m s 15 v cc valid to rst, rst t brst 30 100 150 m s 16
tri +5v st output 3.3 k w 2.2 k w DS1236 022698 19/19 capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf notes: 1. all voltages referenced to ground. a 0.1 m f capacitor is recommended between v cc and gnd. 2. measured with v cco , ceo , pf, st , pbrst , rst, rst , and nmi pin open. i bat specified at 25 c. 3. i cco1 is the maximum average load which the DS1236 can supply at v cc -0.3v through the v cco pin during normal 5-volt operation. 4. i cco2 is the maximum average load which the DS1236 can supply through the v cco pin during data retention battery supply operation, with a maximum drop of 0.8 volts. 5. with t r = 5 m s. 6. v cco is approximately v bat -0.5v at 1 m a load. 7. sleep mode is not invoked. 8. sleep mode is invoked. 9. t rec is the minimum time required before cei /ceo memory access is allowed. 10. t ce maximum must be met to ensure data integrity on power loss. 11. in input is less than v tp but v cc greater than v cctp . 12. all outputs except rst which is 25 m a maximum. 13. all outputs except rst and nmi which is 25 m a minimum. 14. pulse width of nmi requires that the in pin remain below v tp . if the in pin returns to a level above v tp for a period longer than t ipd and before the t nmi period has elapsed, the nmi pin will immediately return to a high. 15. in pin greater than v tp when v cc supply rises to v bat . example: in tied to gnd. 16. in pin less than v tp when v cc supply rises to v bat . 17. cei low. 18. the wc/sc pin contains an internal latch which drives back on to the pin. this latch requires + 200 m amps to switch states. the st pin will sink + 50 uamps in normal operation and + 1 m amp in the sleep mode. 19. st should be active low before the watchdog is disabled (i.e., before the st input is tristated).

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